Working in RCD means being part of a high skilled team spreading from IC design/layout/verification to electrical/irradiation testing. B.Sc./M.Sc. in electrical engineering or physics is mandatory, Ph.D. degree is welcome.
If you are interested in working with us and being part of our journey in the rad-hard components development send your CV to email@example.com mentioning one (or more) of the following codes:
JRCD-19-01: Testing Engineer.
In the framework of internal ATE development for memories and analog components a testing engineer position is available for developing PCBs and writing software tools for rad-hard component testing either in laboratory and under irradiation (Cobalt 60 and Heavy Ions). Skills in software (verilog, vhdl, Visual Basic, Visual Studio, Python) is required to develop both firmware (at FPGA and Microcontroller level) and high level (PC interface). Skills in electrical testing by using oscilloscopes, pattern generators and standard testing equipment is also required.
For this position a B.Sc. or M.Sc. is required.
JRCD-19-02: Layout Engineer.
For internal development of rad-hard standard cells and embedded memory compilers a layout engineer position is available. Skills in major commercial and open source (Open Circuit Design) EDA tools are required. Knowledge in layout physical design and verification is mandatory. For this position is strongly required availability in working in team with IC designers following internal layout rules focused on radiation-hardening.
For this position a B.Sc. is required. M.Sc. is welcome.
JRCD-19-03: Memory Architect.
For internal NVM and SRAM development a memory architect position is available. Skills in Flash and emerging memories (ReRAM in particular) as well as SRAM (Single and Dual Ports) are required. Knowledge of both synchronous and asynchronous memories (including serial memories) is a must. Knowledge in physical design of large arrays and memory cell modeling is a plus.
Skills in commercial and open source EDA tools are required including layout design, simulation, verification, parasitic extraction and back-annotation. Familiarity with verilog/vhdl and abstract generation (including memory characterization) is a plus.
The candidate will report directly with CEO and CTO for development of new products both as stand-alone or embedded macro.
For this position a M.Sc. is required. Ph.D. is welcome.