Synchronous Dual Port SRAMs

DESCRIPTION

RC7CSDP SRAMs are low voltage, high performance, synchronous, rad hard 1k/2k/4k/8k words x 1/8/16bit dual-port memory device using 8T memory cells. The macro is organized with independent addresses and control signals (A and B). The simultaneous access from A and B to the same memory cell is forbidden and A side is the winner with BUSY_1 high (Hard Busy); in case of access on same column or row BUSY_2 is high as warning (Soft Busy). Input addresses and control signals are not latched, so a maximum skew between them must be respected.
Thanks to independent decoding schemes macros have only SEUs (Single Event Upsets) and no MBUs (Multiple Bit Upsets).
A standard 0.18µm CMOS 6 metals technology process has been used to implement.
RC7CSDP SRAMs have a dedicated robust rad-hard by design (RHBD) approach avoiding SEL (Single Event Latch-up) and mitigating TID (Total Ionizing Dose) up to 300 krad (Si).

RC7CSDP SRAMs are delivered with liberty description (.lib), verilog (.v), abstract (.lef) and full extracted netlist for making extended spice and verilog simulations.

RC7CSDP1K1B (1024 x1 DPSRAM)
RC7CSDP1K8B (1024 x8 DPSRAM)
RC7CSDP1K16B (1024 x16 DPSRAM)
RC7CSDP2K1B (2048 x1 DPSRAM)
RC7CSDP2K8B (2048 x8 DPSRAM)
RC7CSDP2K16B (2048 x16 DPSRAM)
RC7CSDP4K1B (4096 x1 DPSRAM)
RC7CSDP4K8B (4096 x8 DPSRAM)
RC7CSDP4K16B (4096 x16 DPSRAM)
RC7CSDP8K1B (8192 x1 DPSRAM)
RC7CSDP8K8B (8192 x8 DPSRAM)
RC7CSDP8K16B (8192 x16 DPSRAM)

Rad Hard 1024 x16 Synchronous Dual Port  SRAM